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CPLD Registers
7
6
5
4
3
2
1
0
R
HRS3
HRS2
HRS1
HRS0
HRC3
HRC2
HRC1
HRC0
W
Reset:
—
—
—
—
0
0
0
0
Figure 7-11. Reset Control and Status Register (RCSR)
Table 7-8. RCSR Bit Descriptions
Bits
7–4
Name
HRS[3–0]
Description
HRESET status from DSP[3–0]. Indicates the state of 0
the HRESET signal from each of the MSC711x
1
Settings
HRESET is asserted.
HRESET is deasserted.
devices.
3–0
HRC[3–0]
HRESET command to DSP[3–0]. Controls the value
0
CPLD does not drive signal.
driven by the CPLD onto each HRESET signal to each 1
MSC711x device.
CPLD asserts signal.
7
6
5
4
3
2
1
0
R
LED
PRST
SWTE
DBRQ
BM3
BM2
BM1
BM0
W
Reset:
0
0
0
0
0
0
0
0
Figure 7-12. Boot Mode Control Register (BMCR)
Table 7-9. BMCR Bit Descriptions
Bits
Name
Description
Settings
7
6
LED
PRST
LED on. Illuminates the LED on the SPT711xPFCE
connected to the CPLD.
Power reset control and status. When read, this bit
0
1
Read:
CPLD LED is not on.
CPLD LED is on.
indicates the state of the PORESET signal to all four
MSC711x devices. When written, this bit controls the
value driven by the CPLD onto the PORESET signal.
0 PORESET is deasserted.
1 PORESET is asserted.
Write:
0 CPLD does not drive signal.
1 CPLD asserts signal.
5
SWTE
SWTE control. Controls the value driven by the CPLD 0
onto the SWTE signal to the MSC711x devices when 1
SWTE is logic low.
SWTE is logic high.
PORESET is asserted.
4
DBRQ
DBREQ control. Controls the value driven by the
CPLD onto the DBREQ signal to the MSC711x
0
1
DBREQ is logic low.
DBREQ is logic high.
devices when PORESET is asserted.
26
3–0
BM[3–0]
BM[3–0] control. Controls the value driven by the CPLD onto the BM[3–0] signals to the
MSC711x devices when PORESET is asserted.
MSC711x Packet Telephony Farm Card (SPT711xPFCE), Rev. 1
Freescale Semiconductor
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